Verification and debugging in complex systems on a chip (SoC) usually utilize trace information from different SoC components. These components may be referred to as trace sources. The trace information may include various trace messages, which may be generated by the trace sources, and are routed through a trace routing network (e.g., a trace network on a chip (NoC)) to a trace output device or interface, which may be referred to as a trace target. The trace target may generate trace protocol and transmit trace information out of the SoC.
In trace analysis, it is significant that trace messages coming from different trace sources have accurate time stamps, for example, a time from a global time stamp may be provided for a trace message at the time of generation. This allows for exacting time correlation, i.e., accurate, among trace messages from different trace sources.
Providing a global time source in a trace target and attaching a time stamp when a trace message arrives at the trace target from a trace source may not be accurate as delays due to random routing and arbitration from the trace source to the trace target, e.g., through a trace routing network, could introduce a time gap between the generation of the trace message and the actual attachment of the time stamp. This may lead to a trace message with an inaccurate time stamp.
Some solutions to this issue suggest attaching the time stamp at the trace source. An implementation of this solution may route a global time stamp value, e.g., thirty-two signals over thirty-two interconnects to each trace source, e.g., to every trace source in the SoC, which would cross different power and clock domains. These interconnects complicate hardware design as the global time stamp lines require isolation and clock synchronization. Additionally, in an environment of increasing on-chip packing densities, routing congestion introduces complex issues.